The present invention relates in general to the field of integrated circuits, and more particularly, to improving across-wafer uniformity of transistor characteristics by reduction of silicon damage caused by gate etch.
Without limiting the scope of the invention, its background is described in connection with the fabrication of Complementary Metal Oxide Semiconductor (xe2x80x9cCMOSxe2x80x9d) devices, as an example. In particular, the background is described in connection with a process for fabricating CMOS devices. In the process of manufacturing CMOS devices, numerous masking and etching steps are required to fabricate the electronic devices on the chip substrate following polysilicon re-oxidation and source/drain implantation.
As is well known in the art of integrated circuit design, layout and fabrication, the manufacturing cost of a given integrated circuit is dependent largely upon the chip area required to implement desired functions. Chip area is defined by the geometries and sizes of the active components disposed in the wafer substrate. Active components include gate electrodes in metal-oxide semiconductors (MOS) and diffused regions such as MOS source and drain regions and bipolar emitters, collectors and base regions.
Present integrated circuit fabrication methodologies require the use of source/drain extensions formed by implantation and diffusion steps, which link source/drain contacts to a channel of a device. Behavioral properties of source/drain extensions are sensitive to factors such as: the amount of oxide on top of the silicon surface, and the amount of damage in the silicon after a polysilicon re-oxidation step. The amount of oxide grown on silicon during a polysilicon re-oxidation step is very sensitive to the amount of damage present. Hence, the source/drain extension properties are very susceptible to variations due to the varying amount of damage in silicon. Therefore, there is a need for increased uniformity of the substrate surface following the formation of features (e.g., gates) that require deep etching steps (e.g., down to the substrate surface). Reduced substrate non-uniformity prior to further processing is also needed, resulting in transistors with both high reliability and high performance without the high cost associated with increased steps or new machinery.
What is needed is a system for producing devices having increased substrate uniformity after gate formation and etch stepsxe2x80x94creating uniform, consistent substrate surfaces for further processing. The system should comprehend the use of existing process equipment, processes and workflows. Finally, a need has arisen for a simplified process for producing more uniform substrate surfaces that is economical using existing techniques and materials.
The present invention recognizes that etch damage to semiconductor device structuresxe2x80x94such as substrates or other semiconductor features, whether formed, deposited, or etchedxe2x80x94causes downstream failure during device processing. The present invention provides a system for fabricating an integrated circuit that provides a semiconductor substrate and forms a gate oxide layer on an active area on the substrate. Next, a polysilicon gate is formed on top of the gate oxide, and etch damage is substantially repaired on the substrate surface. An inert gas repair anneal step is performed prior to subsequent polysilicon processing (e.g., polysilicon re-oxidation). The inert gas repair anneal may be used to decrease non-uniformity caused by exposure to plasma, or by deposition steps (e.g., deposition of polysilicon). It may also be used to decrease the non-uniformity of source/drain implantation of LDD or HDD, which are highly susceptible to scatter in a damaged substrate.